The present invention relates to a metallization process for manufacturing semiconductor devices. More particularly, the present invention relates, to the metallization of apertures to form void-free interconnections between conducting layers, including such contacts or vias in high aspect ratio sub-half micron applications.
Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (xe2x80x9cVLSIxe2x80x9d). The multilevel interconnections that lie at the heart of this technology require planarization of high aspect ratio apertures, including contacts, vias, lines or other features. Reliable formation of these interconnects is very important to the success of VLSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Aluminum (Al) layers formed by chemical vapor deposition (xe2x80x9cCVDxe2x80x9d), like other CVD processes, provide good conformal aluminum layers, i.e., a uniform thickness layer on the sides and base of the feature, for very small geometries, including sub-half micron ( less than 0.5 xcexcm) apertures, at low temperatures. Therefore, CVD of aluminum is a common method used to fill apertures. However, recent transmission electron microscopy data (xe2x80x9cTEMxe2x80x9d) has revealed that voids exist in many of the CVD formed Al apertures even though electric tests of these same apertures do not evidence the existence of this void. If the layer is subsequently processed, the void can result in a defective circuit.
Referring to FIG. 3, a TEM photograph shows a cross-sectional image of a 0.45 micron via filled with CVD Al. The image clearly indicates that voids exist in the metal layer deposited within the via structure. It should be recognized that this kind of void is very difficult to detect by regular cross sectional standard electron microscopy (xe2x80x9cSEMxe2x80x9d) techniques, because some deformation occurs in soft aluminum during mechanical polishing. In addition, electric conductivity tests do not detect any structural abnormalities. However, despite the generally positive electric conductivity tests, conduction through the contact having the void may, over time, compromise the integrity of the integrated circuit devices.
A TEM study of various CVD Al layers formed on substrates indicates that the formation of voids occurs through a key hole process wherein the top portion of the via becomes sealed before the via has been entirely filled. Although a thin conformal layer of CVD Al can typically be deposited in high aspect ratio contacts and vias at low temperatures; continued CVD deposition to complete filing of the contacts or vias typically results in the formation of voids therein. Extensive efforts have been focused on elimination of voids in metal layers by modifying CVD processing conditions. However, the results have not yielded a void free structure.
An alternative technique for metallization of high aspect ratio apertures, is hot planarization of aluminum through physical vapor deposition (xe2x80x9cPVDxe2x80x9d). The first step in this process requires deposition of a thin layer of a refractory metal such as titanium (Ti) on a patterned wafer to form a wetting layer which facilitates flow of the Al during the PVD process. Following deposition of the wetting layer, the next step requires deposition of either (1) a hot PVD Al layer or (2) a cold PVD Al layer followed by a hot PVD Al layer onto the wetting layer. However, hot PVD Al processes are very sensitive to the quality of the wetting layer, wafer condition, and other processing parameters. Small variations in processing conditions and/or poor coverage of the PVD Ti wetting layer can result in incomplete filling of the contacts or vias, thus creating voids. In order to reliably fill the vias and contacts, hot PVD Al processes must be performed at temperatures above about 450xc2x0 C. Because the PVD Ti process provides poor coverage of high aspect ratio, sub-micron via side walls, hot PVD Al does not provide reliable filling of the contacts or vias. Even at higher temperatures, PVD processes may result in a bridging effect whereby the mouth of the contact or via is closed because the deposition layer formed on the top surface of the substrate and the upper walls of the contact or via join before the floor of the contact or via has been completely filled.
Once a PVD Al layer has been deposited onto the substrate, reflow of the Al may occur by directing ion bombardment towards the substrate itself. Bombarding the substrate with ions causes the metal layer formed on the substrate to reflow. This process typical heats the metal layer as a result of the energy created by the plasma and resulting collisions of ions onto the metal layer. The generation of high temperatures of the metal layers formed on the substrate compromises the integrity of devices having sub-half micron geometries. Therefore, heating of the metal layers is disfavored in these applications.
U.S. Pat. No. 5,147,819 (xe2x80x9cthe ""819 patentxe2x80x9d) discloses a process for filling vias that involves applying a CVD Al layer with a thickness of from 5 percent to 35 percent of the defined contact or via diameter to improve step coverage, then applying a sufficiently thick PVD Al layer to achieve a predetermined overall layer thickness. A high energy laser beam is then used to melt the intermixed CVD Al and PVD Al and thereby achieve improved step coverage and planarization. However, this process requires heating the wafer surface to a temperature no less than 660xc2x0 C. Such a high temperature is not acceptable for most sub-half micron technology. Furthermore, the use of laser beams scanned over a wafer may affect the reflectivity and uniformity of the metal layer.
The ""819 patent also discloses that silicide layers and/or barrier metal layers may be deposited onto a wafer before Al is deposited by either a CVD or PVD process. According to the teachings of this reference, these additional underlying layers are desirable to increase electrical conduction and minimize junction spiking.
U.S. Pat. No. 5,250,465 (xe2x80x9cthe ""465 patentxe2x80x9d) discloses a process similar to the ""819 patent using a high energy laser beam to planarize intermixed CVD/PVD metal structures. Alternatively, the ""465 patent teaches the application of a PVD Al layer formed at a wafer temperature of about 550xc2x0 C. However, during the high temperature sputtering process, ion bombardment due to the plasma raises the surface temperature to about 660xc2x0 C. causing the Al film to melt and planarize. Like the process of the ""819 patent, the use of high temperatures is unacceptable for most sub-half micron applications, and particularly for use in filling high aspect ratio sub-half micron contacts and vias. Subjecting wafers to temperatures high enough to melt intermixed CVD/PVD metal layers can compromise the integrity of devices formed on the substrate, in particular where the process is used to planarize a metal layer formed above several other metal and dielectric layers.
Other attempts at filling high aspect ratio sub-half micron contacts and vias using known reflow or planarization processes at lower temperatures have resulted in dewetting of the CVD Al from the silicon dioxide (SiO2) substrate and the formation of discontinuous islands on the side walls of the vias. Furthermore, in order for the CVD Al to resist dewetting at lower temperatures, the thickness of the CVD Al has to be several thousand Angstroms (xc3x85). Since ten thousand Angstroms equal one micron, a CVD Al layer of several thousand Angstroms on the walls of a sub-half micron via will completely seal the via and form voids.
Therefore, there remains a need for a low temperature metallization process for filling apertures, particularly high aspect ratio sub-half micron contacts and vias. More particularly, it would be desirable to have a low temperature process for filling such contacts and via with only a thin layer of CVD Al and allowing the via to then be filled with PVD Al.
The present invention provides a process for providing uniform step coverage on a substrate. First, a thin refractory layer is formed on a substrate followed by a thin conformal CVD metal layer formed over the refractory layer. A PVD metal layer is then deposited over the CVD metal layer.
The present invention relates generally to improved step coverage and planarization of metal layers to form continuous, void-free contacts or vias, including such as in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD Al layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for PVD Al. Next, PVD Al is deposited onto the previously formed CVD Al layer at a temperature below that of the melting point of aluminum. The resulting CVD/PVD Al layer is substantially void-free.
In another aspect of the invention, the metallization process is carried out in an integrated processing system that includes both a PVD and CVD processing chamber. Once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer. This results because the substrate need not be transferred from one processing system to another system to undergo deposition of the CVD and PVD deposited layers. Accordingly, the substrate remains under vacuum pressure thereby preventing formation of detrimental oxide layers. Furthermore, diffusion of dopants deposited with the PVD layer into the CVD layer is improved by simultaneous deposition in the integrated system.
The present invention further provides an apparatus for providing improved step coverage and metallization of a semiconductor . The apparatus comprises a multiplicity of isolatable communicating regions including a load lock chamber, a refractory metal processing chamber, a CVD metal processing chamber, and a PVD metal processing chamber. The apparatus further comprises an intermediate substrate transport region and vacuum means communicating with the isolatable regions for establishing a vacuum gradient of decreasing pressure across the apparatus from the load lock chamber to the processing chambers.